Semiconductor wafers are generally prepared from a single crystal ingot (e.g., a silicon ingot) which is trimmed and ground to have one or more flats or notches for proper orientation of the wafer in subsequent procedures. The ingot is then sliced into individual wafers. While reference will be made herein to semiconductor wafers constructed from silicon, other materials may be used to prepare semiconductor wafers, such as germanium, silicon carbide, silicon germanium, or gallium arsenide.
Semiconductor wafers (e.g., silicon wafers) may be utilized in the preparation of composite layer structures. A composite layer structure (e.g., a silicon-on-insulator (SOI) structure) generally comprises a handle wafer or layer, a device layer, and an insulating (i.e., dielectric) film (typically an oxide layer) between the handle layer and the device layer. Generally, the device layer is between 0.05 and 20 micrometers thick. In general, composite layer structures, such as silicon-on-insulator (SOI), silicon-on-sapphire (SOS), and silicon-on-quartz, are produced by placing two wafers in intimate contact, followed by a thermal treatment to strengthen the bond.
After thermal anneal, the bonded structure undergoes further processing to remove a substantial portion of the donor wafer to achieve layer transfer. For example, wafer thinning techniques, e.g., etching or grinding, may be used, often referred to as back etch SOI (i.e., BESOI), wherein a silicon wafer is bound to the handle wafer and then slowly etched away until only a thin layer of silicon on the handle wafer remains. (See, e.g., U.S. Pat. No. 5,189,500, which is incorporated in its entirety herein by reference.) A particular challenge in the preparation of SOI structures is the presence of warp or bow, particularly when a portion of the buried oxide (BOX) is contributed from the bonding surface of the device wafer. If the BOX thickness is different from (typically more than) the thickness of the oxide on the backside of the support wafer, the SOI wafer will have high warp or bow which can be over the acceptable limit. High warp or bow can cause serious problems, such as handling in SOI wafering and fabrication lines.